1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having an Intellectual property (IP) test circuit to be used for testing the operation of each Intellectual property core (hereinafter referred to as IP) such as logical blocks of USB and JPEG, a DRAM, and other logical blocks.
2. Description of the Related Art
FIG. 1 is a block diagram showing a configuration of a conventional LSI with plural IP (IP-1 and IP-2). In FIG. 1, the reference numbers 113 and 114 designate IP-1 and IP-2, respectively such as logical blocks of a universal serial bus (USB) and JPEG, a DRAM, and so on. The reference number 111 denotes a CPU. The reference numbers 117 and 118 designate test control terminals. The reference number 110 designates a LSI on which the CPU 111, the IP 113, and the IP 114 are mounted.
In the configuration of the conventional semiconductor integrated circuit shown in FIG. 1, the IP 113 is directly connected to the CPU 111, and the IP 114 is not directly connected to the CPU 111. The IP 113 is connected to an external device (omitted from FIG. 1) through the test control terminal 117. The IP 114 is connected to an external device (omitted from FIG. 1) through the test control terminal 118.
Next, a description will be given of the operation of the conventional semiconductor integrated circuit with the IP shown in FIG. 1.
When the test operation of each IP mounted on the LSI shown in FIG. 1 is executed, the external device such as an external tester (not shown) outputs a test program and test data to the semiconductor integrated circuit (as a LSI) having a plurality of IP. After this, the test operation of each IP is executed in the LSI and then the LSI outputs test results of the test operation to the external tester through the test control terminals 117 and 118. In the configuration of the conventional semiconductor integrated circuit as a LSI, the test control terminals are formed per IP. Through the test control terminals 117 and 118 and the IP bus 115 and 116, test data and control signals to be used for testing each IP are transferred between each IP and the external tester.
Because the conventional semiconductor integrated circuit with plural IP has the configuration described above, it is required to form the test control terminal per IP. Accordingly, the conventional semiconductor integrated circuit has tens of test control terminals or hundreds of test control terminals. Because the number of the test control terminals is increased in proportion to the increasing of the number of the IP, the area to be used for the test control terminals is limited in the semiconductor integrated circuit when the test control terminals are formed on the semiconductor integrated circuit. Moreover, it is impossible to test a plurality of semiconductor integrated circuits simultaneously because of the limitation of the area and the number of the test control terminals. Furthermore, it must be required to use an external tester of more expensive when executing At-Speed test.
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional technique, to provide a semiconductor integrated circuit with a IP test circuit that is capable of decreasing the number of test control terminals. Furthermore, the semiconductor integrated circuit with the IP test circuit is capable of executing test operation for the plurality of IP simultaneously even if the semiconductor integrated circuit has the plurality of IP.
In accordance with a preferred embodiment of the present invention, a semiconductor integrated circuit with a IP test circuit comprises a plurality of Intellectual Properties (IP), memory means, a central processing unit (CPU), a test sequencer, and a control means. The memory means stores a test program and test data to be used for test operation of the plurality of IP. The CPU reads the test program and the test data stored in the memory means and executes test operation for the plurality of IP. The test sequencer executes test operation for the IP that is not directly connected to the CPU. The control means has a register and the control means instructs an execution of the test program to the CPU and instructs an execution of the test operation to the test sequencer when a mode value is set into the register.
In the semiconductor integrated circuit with the IP test circuit as another preferred embodiment of the present invention, the memory means is a Random Access Memory (ROM). The IP test circuit further comprises a selector and a bus interface. The selector connects the RAM to the test data terminal in order to read the test program and test data in serial form transferred from an external device through the test data terminal. The bus interface then converts the test program and the test data in serial form received through the test data terminal into the test program and test data in parallel form. In the semiconductor integrated circuit with the IP test circuit, the control means stores the test program and the test data into the RAM transferred through the test data terminal, the selector, and the bus interface from the external device when the mode value is set into the register, and transfers a control signal so that the CPU and the test sequencer execute the test operation for the plurality of IP, and outputs a test result to the external device through the test data terminal.
In the semiconductor integrated circuit with the IP test circuit as another preferred embodiment according to the present invention, the memory means is a Read Only Memory (ROM) in which the test program and the test data are stored beforehand.
In accordance with a preferred embodiment of the present invention, a semiconductor integrated circuit with a IP test circuit comprises a plurality of IP, a memory means, a CPU, a first bus interface, and a control means. The memory means stores a test program and test data to be used for test operation for the plurality of IP. The CPU reads the test program and the test data stored in the memory means and executes test operation for the plurality of IP. The first bus interface connects a cpu bus, that is directly connected to the CPU, to the IP in the plurality of IP that is not directly connected to the cpu bus. The control means having a register instructs to the CPU an execution of the test operation for both the IP directly connected to the CPU and the IP that is not directly connected to the CPU, and also instructs to the first bus controller an execution so that the cpu bus is connected to the IP that is not directly connected to the CPU when a mode value is set into the register.
In the semiconductor integrated circuit with the IP test circuit as another preferred embodiment according to the present invention, the memory means is a Random Access Memory (RAM). The IP test circuit further comprises a second bus interface for connecting the test data terminal to the RAM in order to receive the test program and the test data in serial form transferred from an external device through the test data terminal, and for converting them into the received test program and test data in parallel form, and for storing the test program and test data in parallel form into the RAM. In the semiconductor integrated circuit, the control means instructs the second bus interface so that the RAM is connected to the test data terminal in order to store the test program and the test data into the RAM, and instructs to the CPU an execution of the test operation for the plurality of IP, and transfers a test result to the external device through the test data terminal.
In the semiconductor integrated circuit with the IP test circuit as another preferred embodiment according to the present invention, the memory means is a Read Only Memory (ROM) in which the test program and the test data are stored beforehand.
In accordance with a preferred embodiment of the present invention, a semiconductor integrated circuit with a IP test circuit comprises a plurality of IP, a test sequencer, and control means. In the plurality of IP, one is connected to a Central Processing Unit (CPU), and another is not directly connected to the CPU. The test sequencer connected to each IP executes test operation for the plurality of IP. The control means having a register, instructs an execution of the test operation to the test sequencer when a mode value is set into the register. In the semiconductor integrated circuit, the test sequencer executes the test operation for the plurality of IP based on the instruction from the control means, and then outputs a test result to an external device through the test data terminal.